1. Field of the Invention
The present invention relates to a system-on-a-chip and a power gating circuit thereof.
2. Description of Related Art
Currently, the system-on-a-chip (SOC) applied in telecommunication products or computers is developing in the trend of high performance and portability, so its power consumption has become an important consideration in design. The most effective way to reduce the power consumption of a circuit is to reduce the operating voltage of the circuit. However, if the operating voltage is lowered, the overall performance of the circuit will be lowered accordingly. Therefore, in order to maintain the overall performance of the circuit, threshold voltages of transistors must be lowered, which will lead to an indexed growth of the sub-threshold leakage current.
FIG. 1 is an architectural view showing the architecture of a conventional power gating circuit. In FIG. 1, a plurality of P-type metal oxide semiconductor (PMOS) transistors is used to accomplish the power gating circuit. Through the control of an input signal VS, a system voltage VDD may be determined whether or not to pass through the power gating circuit to serve as an output voltage VVDD, so as to provide the operating power required by a function block 120. Therefore, the system may selectively shut down the function block 120 to reduce the power consumption of the system. However, in FIG. 1, the gate voltage of each PMOS transistor will generate a large transient current during the transition (e.g., changing from a high voltage level to a low voltage level), and the self-inductance generated by the large transient current flowing through the bonding wires and the parasitic inductance in the chip will cause voltage fluctuation of the source line in the chip. If the amplitude of the voltage fluctuation is great, the internal circuit of the function block 120 is often locked at a wrong value, or the circuit transit at a wrong time point, leading to error actions of the function block 120.
In order to solve the problem of voltage fluctuation of the power gating circuit, the following solution is provided. FIG. 2 is a schematic view of a power gating circuit of U.S. Pat. No. 6,876,252B2. Referring to FIG. 2, a plurality of PMOS transistors and a plurality of delayers 210 are used to accomplish the power gating circuit. Firstly, the width-to-length ratio (W/L) of each transistor is designed to be 1/n of the original value. Thus, when the transistors are in the operating state, the output current is 1/n of the original value, i.e., the output current becomes smaller. The power gating circuit has a delayer 210 between the gate terminals of every two transistors, such that the transistors are conducted step by step. Thus, the transistors will not be all conducted at the same time, so as to restrict the transient current of the power gating circuit and reduce the amplitude of voltage fluctuation. However, though the power gating circuit reduces the transient current by conducting the transistors step by step, all the transistors are fully on when being conducted, so the transient current of the power gating circuit is still quite large.
FIG. 3 is a schematic view of a power gating circuit published in Minimizing inductive noise in system-on-a-chip with multiple power gating structures (Proc. of the European Solid-State Circuit Conference, pp. 635-638, September 2003) by Suhwan Kim et al. Referring to FIG. 3, the power gating circuit makes the transistor 310 to enter the operating state slowly by controlling, i.e., gradually reducing the gate voltage of the control transistor 310, such that the transistor 310 generates a small transient current in the operating state. Thus, the voltage fluctuation of the function block 320 is alleviated. However, though the power gating circuit can suppress the voltage fluctuation, the circuit structure is too complicated.